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usbxpress? family CP2102N data sheet the CP2102N devices, part of the usbxpress family, are de- signed to quickly add usb to your applications by eliminating firmware complexity and reducing development time. these highly-integrated usb-to-uart bridge controllers provide a simple solution for updating rs-232 designs to usb using a minimum of components and pcb space. CP2102N includes a usb 2.0 full-speed function controller, usb transceiver, oscillator, and universal asynchronous receiver/transmitter (uart) in packages as small as 3 mm x 3 mm. no other external usb components are required for development. all cus- tomization and configuration options can be selected using a simple gui-based config- urator. by eliminating the need for complex firmware and driver development, the CP2102N devices enable quick usb connectivity with minimal development effort. CP2102N is ideal for a wide range of applications, including the following: key features ? no firmware development required ? simple gui-based configurator ? integrated usb transceiver; no external resistors required ? integrated clock; no external crystal required ? usb 2.0 full-speed compatible ? data transfer rates up to 3 mbaud ? usb battery charger detection (usb bcs 1.2 specification) ? remote wakeup for waking a suspended host ? low operating current : 9.5 ma ? royalty-free virtual com port drivers ? pos terminals ? usb dongles ? gaming controllers ? medical equipment ? data loggers external rs-232 transceiver or uart circuitry external circuitry for usb suspend states CP2102N 48 mhz oscillator usb battery charger detect remote wakeup usb connector external battery charging circuitry voltage regulator usb function controller 512 byte rx buffer 960 byte configuration memory uart hardware handshaking rs485 usb transceiver 512 byte tx buffer feature is related to: uart usb overall system silabs.com | smart. connected. energy-friendly. rev. 1.0
1. feature list and ordering information 2102n C a C r tape and reel (optional) package type qfn20, qfn24, or qfn28 firmware revision hardware revision 01 cp g qfn20 temperature grade C40 to +85 c (g) silicon labs xpress product line usbxpress family, usb-to-uart bridge figure 1.1. CP2102N part numbering the CP2102N devices have the following features: ? single-chip usb-to-uart data transfer ? integrated usb transceiver; no external resistors required ? integrated clock; no external crystal required ? internal 960-byte programmable rom for vendor id, prod- uct id, serial number, power descriptor, release number, and product description strings ? on-chip power-on reset circuit ? on-chip voltage regulator 3.3 v output ? pin compatible with cp2101/2/9 (qfn28 package) ? pin compatible with cp2104 (qfn24 package) ? usb function controller ? usb specification 2.0 compliant; full-speed (12 mbps) ? usb suspend states supported via suspend pins ? usb battery charger detection (usb bcs 1.2 specifica- tion) ? remote wakeup for waking a suspended host ? single power supply of 2.2 to 3.6 v or 3.0 to 5.25 v ? universal asynchronous receiver/transmitter (uart) ? all handshaking and modem interface signals ? data formats supported ? data bits 5, 6, 7, and 8 ? stop bits 1, 1.5, and 2 ? parity odd, even, mark, space, no parity ? baud rates: 300 baud to 3 mbaud ? 512 byte receive buffer ? 512 byte transmit buffer ? hardware or xon/xoff handshaking supported ? virtual com port device drivers ? works with existing com port applications ? supported on windows, mac, and linux ? royalty-free distribution license ? usbxpress? direct driver support ? royalty-free distribution license table 1.1. product selection guide ordering part number gpios battery charger detect separate vio and vdd pins pb-free (rohs compliant) temperature range package CP2102N-a01-gqfn28 7 yes yes -40 to +85 c qfn28 CP2102N-a01-gqfn24 4 yes yes -40 to +85 c qfn24 CP2102N-a01-gqfn20 4 yes -40 to +85 c qfn20 CP2102N data sheet feature list and ordering information silabs.com | smart. connected. energy-friendly. rev. 1.0 | 1
2. typical connection diagrams 2.1 power in all cases, a 1 k ? pull-up on the rstb pin is recommended. this pull-up should be tied to vio on devices that have it. on devices where vio is connected to vdd or devices that do not have vio, this pull-up should be tied to vdd. the figure below shows a typical connection diagram for the power pins of the CP2102N devices when the internal regulator is used and usb is connected (bus-powered). CP2102N device voltage regulator vregin gnd 4.7 f and 0.1 f bypass capacitors required for each power pin placed as close to the pins as possible. 3.3 v (out) vdd usb 5 v (in) rstb vio figure 2.1. connection diagram with voltage regulator used and usb connected (bus-powered) the figure below shows a typical connection diagram for the power pins of the CP2102N devices when the internal regulator is used and usb is connected (self-powered). CP2102N device voltage regulator vregin gnd 4.7 f and 0.1 f bypass capacitors required for each power pin placed as close to the pins as possible. 3.3 v (out) vdd 3.6-5.25 v (in) rstb vio figure 2.2. connection diagram with voltage regulator used and usb connected (self-powered) CP2102N data sheet typical connection diagrams silabs.com | smart. connected. energy-friendly. rev. 1.0 | 2
the figure below shows a typical connection diagram for the power pins of the CP2102N devices when the internal 5 v-to-3.3 v regula- tor is not used. CP2102N device voltage regulator 2.2-3.6 v (in) gnd 4.7 f and 0.1 f bypass capacitors required for each power pin placed as close to the pins as possible. vregin vdd rstb vio 1 kohm figure 2.3. connection diagram with voltage regulator not used CP2102N data sheet typical connection diagrams silabs.com | smart. connected. energy-friendly. rev. 1.0 | 3
2.2 battery charger detect the CP2102N battery charger detect notifies an external battery charger the amount of current available from the usb interface. the figure below shows an example connection diagram for external battery charging circuitry. if using an external battery charging ic, consult the data sheet for more information about the specific recommended connection diagrams. CP2102N device d+ gnd vregin d- usb connector vbus d+ signal gnd d- vbus chr1 (1.5 a) chr0 (500 ma) chren (100 ma) external battery charging ic seti cen sp0503baht or equivalent usb esd protection diodes (recommended) figure 2.4. battery charging connection diagram CP2102N data sheet typical connection diagrams silabs.com | smart. connected. energy-friendly. rev. 1.0 | 4
2.3 usb the figure below shows a typical connection bus-powered diagram for the usb pins of the CP2102N devices including esd protection diodes on the usb pins. CP2102N device usb d+ gnd vregin d- usb connector vbus d+ signal gnd d- sp0503baht or equivalent usb esd protection diodes (recommended) vbus figure 2.5. bus-powered connection diagram for usb pins the figure below shows a typical connection self-powered diagram for the usb pins of the CP2102N devices including esd protection diodes on the usb pins. note: there are two relevant restrictions on the vbus pin voltage in this self-powered configuration. the first is the absolute maximum voltage on the vbus pin, which is defined as vio + 2.5 v in table 3.10 absolute maximum ratings on page 12 . the second is the input high voltage (vih) for vbus to detect when the device is connected to a bus, which is defined as vio C 0.6 v in table 3.7 gpio on page 10 . for self-powered systems where vdd and vio may be unpowered when vbus is connected to 4.4 v to 5.5 v, a resistor divider (or functionally-equivalent circuit) on vbus is required to meet these specifications and ensure reliable device operation. in this case, the current limitation of the resistor divider prevents high vbus pin leakage current, even though the vio + 2.5 v specification is not strictly met. CP2102N data sheet typical connection diagrams silabs.com | smart. connected. energy-friendly. rev. 1.0 | 5
CP2102N device usb d+ gnd vbus d- usb connector vbus d+ signal gnd d- sp0503baht or equivalent usb esd protection diodes (recommended) 22.1 k? 47.5 k? figure 2.6. self-powered connection diagram for usb pins CP2102N data sheet typical connection diagrams silabs.com | smart. connected. energy-friendly. rev. 1.0 | 6
3. electrical specifications 3.1 electrical characteristics all electrical parameters in all tables are specified under the conditions listed in table 3.1 recommended operating conditions on page 7 , unless stated otherwise. 3.1.1 recommended operating conditions table 3.1. recommended operating conditions parameter symbol test condition min typ max unit operating supply voltage on vdd 1 v dd 2.2 3.6 v operating supply voltage on vio 3 v io 1.71 v dd v operating supply voltage on vre- gin v regin 3.0 5.25 v operating ambient temperature t a -40 85 c note: 1. standard usb compliance tests require 3.0 v on vdd for compliant operation. 2. all voltages with respect to gnd. 3. on devices without a vio pin, v io = v dd . 4. gpio levels are undefined whenever vio is less than 1 v. 3.1.2 power consumption table 3.2. power consumption parameter symbol test condition min typ max unit normal operation 1, 2 i dd 115200 baud transmitting continu- ous bidirectional data 9.5 ma 3 mbaud transmitting continuous bidirectional data 13.7 ma usb suspend 1, 2 i dd 195 a held in reset 1, 2 i dd 1.3 ma usb pull-up 3 i pu 200 230 a note: 1. includes supply current from internal ldo regulator, supply monitor, and internal oscillators. these power consumption numbers are only for the CP2102N and do not include an external rs232 transceiver or other external circuitry. 2. usb pull-up current should be added for total supply current. normal and suspended supply current is current flowing into vre- gin. 3. the usb pull-up supply current values are calculated values based on usb specifications. usb pull-up supply current is current flowing from vdd to gnd through usb pull-down/pull-up resistors on d+ and d-. CP2102N data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 7
3.1.3 reset and supply monitor table 3.3. reset and supply monitor parameter symbol test condition min typ max unit vdd supply monitor threshold v vddm 1.95 2.05 2.15 v power-on reset (por) threshold v por rising voltage on vdd 1.2 v falling voltage on vdd 0.75 1.36 v vdd ramp time t rmp time to v dd > 2.2 v 10 s reset delay from por t por relative to v dd > v por 3 10 31 ms reset delay from non-por source t rst time between release of reset source and code execution 50 s rstb low time to generate reset t rstl 15 s 3.1.4 configuration memory table 3.4. configuration memory parameter symbol test condition min typ max units v dd voltage during programming 1 v prog 2.2 3.6 v endurance (write/erase cycles) n we 20k 100k cycles note: 1. the device can be safely programmed at any voltage above the supply monitor threshold (v vddm ). 2. data retention information is published in the quarterly quality and reliability report. 3.1.5 internal oscillator table 3.5. internal oscillator parameter symbol test condition min typ max unit internal oscillator frequency f osc full temperature and supply range 47.3 48 48.7 mhz power supply sensitivity pss osc t a = 25 c 0.02 %/v temperature sensitivity ts osc v dd = 3.0 v 45 ppm/c CP2102N data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 8
3.1.6 5 v voltage regulator table 3.6. 5v voltage regulator parameter symbol test condition min typ max unit input voltage range 1 v regin 3.0 5.25 v output voltage on vdd 2 v regout output current = 1 to 100 ma regulation range (vregin 4.1v) 3.1 3.3 3.6 v output current = 1 to 100 ma dropout range (vregin < 4.1v) v regin C v dropout v output current 2 i regout 100 ma dropout voltage v dropout output current = 100 ma 0.8 v note: 1. input range to meet the output voltage on vdd specification. if the 5 v voltage regulator is not used, vregin should be tied to vdd. 2. output current is total regulator output, including any current required by the device. CP2102N data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 9
3.1.7 gpio table 3.7. gpio parameter symbol test condition min typ max unit output high voltage (high drive) v oh i oh = -7 ma, v io 3.0 v v io - 0.7 v i oh = -3.3 ma, 2.2 v v io < 3.0 v i oh = -1.8 ma, 1.71 v v io < 2.2 v v io x 0.8 v output low voltage (high drive) v ol i ol = 13.5 ma, v io 3.0 v 0.6 v i ol = 7 ma, 2.2 v v io < 3.0 v i ol = 3.6 ma, 1.71 v v io < 2.2 v v io x 0.2 v output high voltage (low drive) v oh i oh = -4.75 ma, v io 3.0 v v io - 0.7 v i oh = -2.25 ma, 2.2 v v io < 3.0 v i oh = -1.2 ma, 1.71 v v io < 2.2 v v io x 0.8 v output low voltage (low drive) v ol i ol = 6.5 ma, v io 3.0 v 0.6 v i ol = 3.5 ma, 2.2 v v io < 3.0 v i ol = 1.8 ma, 1.71 v v io < 2.2 v v io x 0.2 v input high voltage (all gpio pins including vbus) v ih v io - 0.6 v input low voltage (all gpio including vbus) v il 0.6 v pin capacitance c io 7 pf weak pull-up current (v in = 0 v) i pu v dd = 3.6 -30 -20 -10 a input leakage (pullups off or ana- log) i lk gnd < v in < v io -1.1 1.1 a input leakage current with v in above v io i lk v io < v in < v io +2.0 v 0 5 150 a rs485 setup time before start bit 1 t rs485s 0 64.02 ms rs485 hold time after stop bit 1 t rs485h 0 64.02 ms tx toggle rate 20 hz rx toggle rate 20 hz note: 1. programmable from 0 ms to 64 ms in 1 s steps. the programmed time is the guaranteed minimum, and the actual time may be up to 20 s longer. CP2102N data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 10
3.1.8 usb transceiver table 3.8. usb transceiver parameter symbol test condition min typ max unit transmitter output high voltage v oh v dd 3.0v 2.8 v output low voltage v ol v dd 3.0v 0.8 v output crossover point v crs 1.3 2.0 v output impedance z drv driving high driving low 28 28 36 36 44 44 pull-up resistance r pu full speed (d+ pull-up) 1.425 1.5 1.575 k output rise time t r full speed 4 20 ns output fall time t f full speed 4 20 ns receiver differential input sensitivity v di | (d+) - (d-) | 0.2 v differential input common mode range v cm 0.8 2.5 v input leakage current i l pullups disabled <1.0 a refer to the usb specification for timing diagrams and symbol definitions. 3.2 thermal conditions table 3.9. thermal conditions parameter symbol test condition min typ max unit thermal resistance ja qfn20 packages 60 c/w qfn24 packages 30 c/w qfn28 packages 26 c/w note: 1. thermal resistance assumes a multi-layer pcb with any exposed pad soldered to a pcb pad. CP2102N data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 11
3.3 absolute maximum ratings stresses above those listed in 3.3 absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specifica- tion is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. for more information on the available quality and reliability data, see the quality and reliability monitor report at http://www.silabs.com/support/quality/pages/ default.aspx . table 3.10. absolute maximum ratings parameter symbol test condition min max unit ambient temperature under bias t bias -55 125 c storage temperature t stg -65 150 c voltage on vdd v dd gnd-0.3 4.2 v voltage on vio 2 v io gnd-0.3 4.2 v voltage on vregin v regin gnd-0.3 5.8 v voltage on d+ or d- v usbd gnd-0.3 v dd +0.3 v voltage on uart pins, gpio, vbus, rstb, or any other non-power, non- usb pin v in v io > 3.3 v gnd-0.3 5.8 v v io < 3.3 v gnd-0.3 v io +2.5 v total current sunk into supply pin i vdd 400 ma total current sourced out of ground pin i gnd 400 ma current sourced or sunk by any uart pins, gpio, vbus, rstb, or any other non-power, non-usb pin i io -100 100 ma operating junction temperature t j -40 105 c note: 1. exposure to maximum rating conditions for extended periods may affect device reliability. 2. on devices without a vio pin, v io = v dd CP2102N data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 12
3.4 typical performance curves figure 3.1. typical v oh curves figure 3.2. typical v ol curves CP2102N data sheet electrical specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 13
4. functional description 4.1 usb function controller and transceiver the universal serial bus function controller in the CP2102N is a usb 2.0 compliant full-speed device with integrated transceiver and on-chip matching and pull-up resistors. the usb function controller manages all data transfers between the usb and the uart as well as command requests generated by the usb host controller and commands for controlling the function of the uart. the usb suspend and resume signals are supported for power management of both the CP2102N device as well as external circuitry. the CP2102N will enter suspend mode when suspend signaling is detected on the bus. on entering suspend mode, the CP2102N asserts the suspend and suspendb signals. suspend and suspendb are also asserted after a CP2102N reset until device con- figuration during usb enumeration is complete. the CP2102N exits suspend mode when any of the following occur: 1. resume signaling is detected or generated. 2. a usb reset signal is detected. 3. a device reset occurs. 4. usb remote wakeup functionality is enabled and the wakeup pin is grounded. on exit of suspend mode, the suspend and suspendb signals are de-asserted. both suspend and suspendb temporarily float high during a CP2102N reset. if this behavior is undesirable, a strong pull-down (10 k ? ) can be used to ensure suspendb remains low during reset. 4.2 universal asynchronous receiver/transmitter (uart) interface the CP2102N uart interface consists of the tx (transmit) and rx (receive) data signals as well as the rts, cts, dsr, dtr, dcd, and ri control signals. the uart supports rts/cts, dsr/dtr, and xon/xoff handshaking. the uart is programmable to support a variety of data formats and baud rates. if the virtual com port drivers are used, the data format and baud rate are set during com port configuration on the pc. if the usbxpress drivers are used, the CP2102N is configured through the usbxpress api. the data formats and baud rates available are listed in the table below. table 4.1. data formats and baud rates parameter available values data bits 5, 6, 7, and 8 stop bits 1, 1.5 1 , and 2 party types none, even, odd, mark, space baud rates 300, 600, 1200, 1800, 2400, 4000, 4800, 7200, 9600, 14400, 16000, 19200, 28800, 38400, 51200, 56000, 57600, 64000, 76800, 115200, 128000, 153600, 230400, 250000, 256000, 460800, 500000, 576000, 921600, 1000000, 1200000, 1500000, 2000000, 3000000 note: 1. 5-bit only. CP2102N data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 14
4.2.1 baud rate generation the baud rate generator is very flexible, allowing the user to request any baud rate in the range from 300 baud to 3 mbaud. if the baud rate cannot be directly generated from the 48 mhz oscillator, the device will choose the closest possible option. the actual baud rate is dictated by the following equations. clock divider = 48 mhz 2 prescale requested baud rate actual baud rate = 48 mhz 2 prescale clock divider in both cases, the prescale value is 4 if the requested baud rate is 365 baud and 1 if the requested baud rate value is > 365 baud. most baud rates can be generated with an error of less than 1.0%. a general rule of thumb for the majority of uart applications is to limit the baud rate error on both the transmitter and the receiver to no more than 2%. the clock divider value is rounded to the near- est integer, which may produce an error source. another error source will be the 48 mhz oscillator, which is accurate to 0.25%. know- ing the actual and requested baud rates, the total baud rate error can be found using the equation below. baud rate error (%) = 100 ( 1 C actual baud rate requested baud rate ) 0.25% 4.3 additional features 4.3.1 general purpose input/outputs (gpio) the CP2102N has up to 7 gpio that can be controlled from the host. by default and during reset, these pins are set to open-drain with a weak pull-up enabled and the port latch set to 1. the pins can be made push-pull to drive external circuitry like leds. in addition, the state of these pins can be configured during standard operation, during suspend, and immediately following reset. note: all pins temporarily float high during a device reset. if this behavior is undesirable, a strong pull-down (10 k ? ) can be used to ensure the pin remains low during reset. the gpio pins may also have alternate functions which are listed in the table below. table 4.2. gpio pin alternate functions gpio pin qfn28 package qfn24 package qfn20 package gpio.0 txt txt clk 1 gpio.1 rxt rxt rs485 gpio.2 rs485 rs485 txt gpio.3 wakeup wakeup rxt gpio.4 no alternate function not available not available gpio.5 no alternate function not available not available gpio.6 no alternate function not available not available note: 1. on qfn28 and qfn24 packages, the clk signal is available on the same pin as ri. by default, all of the gpio pins are configured as a gpio input. the speed of reading and writing the gpio pins is subject to the timing of the usb bus. gpio pins configured as inputs or outputs are not recommended for real-time signaling. more information regarding the configuration of these pins can be found in xpress configurator in simplicity studio and an721: cp21xx device customization guide . guidance on gpio usage can be found in an223: runtime gpio control for cp210x . CP2102N data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 15
4.3.2 dynamic suspend by default, the latch values for all pins remains static during usb suspend. alternatively, the dynamic suspend feature sets the pin latch to a predefined state when the CP2102N device moves from the config- ured usb state to the suspend usb state (see chapter nine of usb 2.0 specification for more information on usb device states). when the device exits the suspend usb state, the pin latch is restored to the previous value before entering the suspend state. dynamic suspend is configured separately for the gpio pins and uart/modem control pins. 4.3.3 output mode each pin has two options for the output mode: push-pull and open-drain. by configuring for push-pull operation, a pin operates as a push-pull output. the output voltage is determined by pins latch value. this type of output is most often used to connect directly to another device or drive external circuitry like an led. by configuring for open-drain operation, a pin operates as an open-drain output or input. the output voltage is determined by the pin's latch value. if the pin latch value is 1, the pin is pulled up to vio (or vdd if the device does not have a vio pin) through an on-chip pull- up resistor. open-drain outputs are typically used when interfacing to logic at a higher voltage than the vio pin. these pins can be safely pulled to the higher, external voltage through an external pull-up resistor if vdd meets the 3.3 absolute maximum ratings re- quirements. 4.3.4 battery charging (chren, chr0, and chr1) when battery charging is enabled, the d+/d- signals will detect the type of current source attached and set the chren, chr0, and chr1 pins appropriately. chren enables 100 ma source current, chr0 enables 500 ma source current, and chr1 enables 1.5 a source current. the charging system may draw up to the limit specified by chren, chr0, and chr1. if the system also is operational while charging, the current set points for the iset resistors should be decreased based on how much the system could be using during battery charge. 4.3.5 remote wakeup (wakeup) the wakeup pin is an optional active low remote wakeup input. when the wakeup pin toggles from inactive to active (i.e. grounded) and the CP2102N is in usb suspend, the CP2102N will begin the wakeup sequence. host software must enable usb remote wakeup for the device. in windows, this is under device manager. to set this, right-click on the device, select [ properties ]>[ power management ] and enable the [ allow this device to wake the computer ] feature. 4.3.6 clock output (clk) an optional clock output is available on CP2102N devices. f clk = 48 mhz 2 n the valid values for n are 1 to 256. CP2102N data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 16
4.3.7 hardware handshaking (rts and cts) to utilize the functionality of the rts and cts pins of the CP2102N , the device must be configured to use hardware flow control on the usb host. rts, or ready to send, is an active-low output from the CP2102N and indicates to the external uart device that the CP2102Ns uart rx fifo has not reached the flow off watermark level of 448 bytes and is ready to accept more data. when the amount of data in the rx fifo reaches the watermark, the CP2102N pulls rts high to indicate to the external uart device to stop sending data. the CP2102N does not pull rts low again until the uart rx fifo is at the flow on watermark level of 384 bytes (at least 128 free bytes). this hysteresis allows for optimal operation. these rts watermark levels are configurable using xpress configurator in simplic- ity studio. cts, or clear to send, is an active-low input to the CP2102N and is used by the external uart device to indicate to the CP2102N when the external uart devices rx fifo is getting full. the CP2102N will not send more than two bytes of data once cts is pulled high. hardware handshaking allows for optimal continuous transmission speeds at high baud rates (greater than 1 mbaud). the effective throughput depends on usb bus loading and host usb stack efficiency. the typical maximum continuous bidirectional data transfer is > 450 kbytes/s at 3 mbaud. rs232 system CP2102N tx rx tx rx rts cts rts cts figure 4.1. using hardware flow control with the CP2102N 4.3.8 software handshaking the CP2102N also supports software handshaking using the xon and xoff event characters. the characters used for xon/xoff is set by the host software. if the CP2102N receives an xoff request, it will stop transmission, even if the CP2102N receiver needs to transmit an xoff over uart. this can potentially allow an overflow to occur or a deadlock condition if both the CP2102N and the connected uart device transmit xoff at the same time. the xoff_continue setting allows the CP2102N transmitter to send xoff/xon requests even if it has received an xoff request from the connected uart device. once the connected uart device transmits xon, normal transmis- sion from the CP2102N resumes. software handshaking uses the same watermark levels as hardware handshaking and can be configured dynamically by host software. watermark levels greater than 512 are converted to an xon limit of 448 bytes and an xoff limit of 512 bytes. if the xon limit crosses over the xoff limit, the xon limit will automatically be modified to not cross over the xoff limit. an xoff limit of 0 is converted to 64 to guarantee buffer space is available until the uart end device stops transmission. when setting the xon and xoff limits, it's rec- ommended to use values where the xon limit added to the xoff limit is less than 512 bytes, like 192/192 or 128/128. CP2102N testing shows that the xon limit set to 192 and xoff limit set to 192 provides optimal software flow control behavior. 0xf0 rs232 system CP2102N tx rx 0x40 0x23 0x51 0x64 0x87 CP2102N receives xon CP2102N receives xoff figure 4.2. software flow control timing diagram CP2102N data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 17
4.3.9 data throughput optimization effective throughput depends on several factors: ? CP2102N placement on the physical usb device tree ? usb bus load from other devices ? host os usb stack efficiency ? CP2102N configuration options handshaking is required at high baud rates (greater than 1 mbaud) to avoid receiver overrun. a request to stop transmission is only initiated once the rx fifo has reached the flow off watermark level. once the usb bus lowers the rx fifo level below the flow on watermark, a request to continue transmission is sent. hardware handshaking allows for optimal continuous transmission speeds at high baud rates. using a windows host pc, the CP2102N's typical maximum continuous bidirectional throughput is > 450 kbytes/s at 3 mbaud (> 70% efficiency). software handshaking using xon/xoff transmission requires more overhead. using a windows host pc, the CP2102N's typical maxi- mum continuous bidirectional throughput is > 330 kbytes/s at 3 mbaud (> 55% efficiency). for these performance numbers, the CP2102N is placed on a usb hub connected to the windows host pc with a third party uart adapter. the only significant usb traffic is generated by the usb to uart devices. the windows host pc is running automated tests with minimal cpu load. certain conditions will reduce the maximum throughput at high baud rates (> 1mbaud): ? using dsr, dtr, or dcd handshaking signals lowers maximum performance. use hardware cts/rts only for peak performance. ? embedded events or error character insertion requires free space in the uart rx fifo to post events to the host. at high baud rates with continuous data reception, this space may not be available. limit maximum baud rates with continuous data reception to 1 mbaud when using embedded events or error character insertion to guarantee reception of events or the error character. ? transmitting an immediate character momentarily causes lower bidirectional throughput as the character forces a bypass of the cur- rent transmit fifo. once the character has been transmitted, the typical bidirectional throughput is restored. using remote wakeup, charge enable, clock out, or the gpios will not impact uart throughput. 4.3.10 transmit and receive led toggles (txt and rxt) the tx and rx led toggle pins will toggle on and off at a fixed rate specified in table 3.7 gpio on page 10 whenever a byte is trans- mitted or received by the CP2102N . these pins are logic high whenever a device is not transmitting or receiving data and can directly drive basic leds within the device specification limits. CP2102N txt rxt vio figure 4.3. transmit and receive toggle CP2102N data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 18
4.3.11 modem control (dsr, dtr, dcd, ri) the modem control pins are enabled when requested on the host. if the virtual com port drivers are used, the modem control pins are enabled during com port configuration on the pc. if the usbxpress drivers are used, the CP2102N is configured through the usbx- press api. the behavior of the modem control pins may vary between operating systems. table 4.3. modem control signals modem control signal description dsr input to the CP2102N. data set ready control input (active low). dtr output from the CP2102N. data terminal ready control output (active low). note that this pin may toggle when opening a com port on some operating systems. dcd input to the CP2102N. data carrier detect control input (active low). ri input to the CP2102N. ring indicator control input (active low). 4.3.12 rs485 (rs485) the rs485 pin is an optional control pin that can be connected to the de and re inputs of the transceiver. when configured for rs485 mode, the pin is asserted during uart data transmission. the rs485 pin is active-high by default and is also configurable for active- low mode using xpress configurator. the rs485 pin setup and hold times are programmable using xpress configurator to enable maximum flexibility. rs485 transceiver CP2102N r d de re tx rx rs485 figure 4.4. using the CP2102N with a rs485 transceiver start d0 d1 d2 d3 ... dn stop tx rs485 rs485 setup (t rs485s ) rs485 hold (t rs485h ) figure 4.5. rs485 output timing diagram for a single-byte transfer 4.4 drivers there are two sets of device drivers available for the CP2102N devices: the virtual com port (vcp) drivers and the usbxpress direct access drivers. only one set of drivers is necessary to interface with the device. the latest drivers are available at www.silabs.com/interface-software . CP2102N data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 19
4.4.1 virtual com port (vcp) drivers the CP2102N virtual com port (vcp) device drivers allow a CP2102N -based usb device to appear to the pc's application software as a com port. application software running on the pc accesses the CP2102N -based device as it would access a standard hardware com port. however, actual data transfer between the pc and the CP2102N device is performed over the usb interface. therefore, existing com port applications may be used to transfer data via the usb to the CP2102N -based device without modifying the applica- tion. see an197: serial communications guide for the cp210x for example code for interfacing to a CP2102N using the virtual com drivers. note: because the CP2102N uses a usb-based communication interface, timing will not be controllable or guaranteed as it is with a standard com port. full-speed usb operates on 1 ms frames, and the host schedules packets for each usb device where it can in the 1 ms frame. it is recommended to use large data transfers when reading and writing from the host to send data as quickly as possible. 4.4.2 usbxpress drivers the silicon labs usbxpress drivers provide an alternate solution for interfacing with CP2102N devices. no serial port protocol exper- tise is required. instead, a simple, high-level application program interface (api) is used to provide simpler cp210x connectivity and functionality. the usbxpress for cp210x development kit includes windows device drivers, windows device driver installer and unin- stallers, and a host interface function library (host api) provided in the form of a windows dynamic link library (dll). the usbxpress driver set is recommended for new products that also include new pc software. the usbxpress interface is described in an169: usbxpress? programmer's guide . 4.4.3 customization and certification in addition to customizing the device as described in 4.5 device customization , the drivers can be also be customized. see an220: usb driver customization for more information on generating customized vcp and usbxpress drivers. the default drivers that are shipped with the CP2102N are microsoft whql (windows hardware quality labs) certified. the certifica- tion means that the drivers have been tested by microsoft and their latest operating systems will allow the drivers to be installed without any warnings or errors. some installations of windows will prevent unsigned drivers from being installed at all. the customized drivers that are generated using the an220 software are not automatically certified. they must first go through the microsoft driver reseller submission process. see an807: recertifying a customized windows hck driver package for more information and contact silicon labs support for assistance with this process. CP2102N data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 20
4.5 device customization the CP2102N includes an internal electrically erasable programmable read-only memory (eeprom). this memory may be used to customize the usb vendor id (vid), product id (pid), product description string, power descriptor, device release number and de- vice serial number as desired for oem applications. if the eeprom is not programmed with oem data, the default configuration data shown in the table below is used. table 4.4. default usb configuration data name description default value vendor id (vid) the vendor id is a four digit hexadecimal number that is unique to a particular vendor. 0x10c4, for example, is the silicon labs vendor id. 0x10c4 product id (pid) the product id is a four digit hexadecimal number that identifies the vendor's device. 0xea60, for example, is the default product id for silicon labs' cp210x usb to uart bridge devices. 0xea60 power mode this setting determines whether the device is bus-pow- ered, i.e. it is powered by the host, or self-powered, i.e. it is powered from a supply on the device. 0x80 (bus-powered) max power this describes the maximum amount of power that the de- vice will draw from the host in ma multiplied by 2. for ex- ample, 0x32 equates to 100 ma. 0x32 release version the release version is a binary-coded-decimal value that is assigned by the device manufacturer. 0x0100 serial string the serial string is an optional string that is used by the host to distinguish between multiple devices with the same vid and pid combination. it is limited to 63 characters. 128-bit unique id assigned by silicon labs product string the product string is an optional string that describes the product. it is limited to 126 characters. "CP2102N usb to uart bridge controller" while customization of the usb configuration data is optional, it is recommended to customize the vid/pid combination. a unique vid/pid combination will prevent the driver from conflicting with any other usb driver. a vendor id can be obtained from http:// www.usb.org/ or silicon labs can provide a free pid for the oem product that can be used with the silicon laboratories vid ( http:// www.silabs.com/products/mcu/pages/request-pid.aspx ). if the oem application supports multiple CP2102N -based devices attached to the same pc, each CP2102N must have a unique serial number. by default, the CP2102N uses a unique 128 bit identifier as the serial number. alternatively, sequential serial numbers can be pre-programmed by silicon labs using settings provided by xpress configurator and delivered as a custom CP2102N part number. these serial numbers can be unique per custom part number, or multiple part numbers can share the same group of sequential serial numbers. for more details, see xpress configurator in simplicity studio. the internal programmable rom is programmed via the usb. this allows the oem's usb configuration data and serial number to be written to the CP2102N on-board rom during the manufacturing and testing process. a simple gui-based or command-line customiza- tion utility for programming the internal programmable rom is available from silicon labs as a part of simplicity studio or available separately on the silicon labs website ( www.silabs.com/interface-software ). the device parameters can be locked to prevent future modification on the CP2102N. CP2102N data sheet functional description silabs.com | smart. connected. energy-friendly. rev. 1.0 | 21
5. pin definitions 5.1 CP2102N qfn28 pin definitions 28 pin qfn (top view) 28 27 26 25 1 2 3 4 8 9 10 11 21 20 19 18 dcd ri / clk gnd d+ vbus rstb nc suspendb gpio.5 gpio.6 gpio.0 / txt gpio.1 / rxt dtr dsr txd rxd gnd 24 23 22 cts gpio.4 12 13 14 suspend chren chr1 5 6 7 17 16 15 d- vdd vregin gpio.2 / rs485 gpio.3 / wakeup chr0 rts 28 pin qfn (top view) figure 5.1. CP2102N qfn28 pinout table 5.1. pin definitions for CP2102N qfn28 pin number pin name description 1 dcd digital input. data carrier detect control input (active low). 2 ri / clk digital input. ring indicator control input (active low). digital output. clock output. 3 gnd ground CP2102N data sheet pin definitions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 22
pin number pin name description 4 d+ usb data positive 5 d- usb data negative 6 vdd supply power input / 5v regulator output 7 vregin 5v regulator input 8 vbus digital input. vbus sense input. this pin should be connected to the vbus signal of a usb network. a 5 v signal on this pin indicates a usb network connection. 9 rstb active-low reset 10 nc no connect (leave this pin floating). 11 suspendb digital output. this pin is driven low when the device enters the usb suspend state. 12 suspend digital output. this pin is driven high when the device enters the usb suspend state. 13 chren digital output. enable charging circuit (100 ma). 14 chr1 digital output. enable highest current (1.5 a). 15 chr0 digital output. enable higher current (500 ma). 16 gpio.3 / wakeup digital input/output. general purpose i/o. digital input. remote usb wakeup interrupt input. 17 gpio.2 / rs485 digital input/output. general purpose i/o. digital output. rs485 control signal. 18 gpio.1 / rxt digital input/output. general purpose i/o. digital output. receive led toggle. 19 gpio.0 / txt digital input/output. general purpose i/o. digital output. transmit led toggle. 20 gpio.6 digital input/output. general purpose i/o. 21 gpio.5 digital input/output. general purpose i/o. 22 gpio.4 digital input/output. general purpose i/o. 23 cts digital input. clear to send control input (active low). 24 rts digital output. ready to send control output (active low). 25 rxd digital input. asynchronous data input (uart receive). 26 txd digital output. asynchronous data output (uart transmit). 27 dsr digital input. data set ready control input (active low). 28 dtr digital output. data terminal ready control output (active low). center gnd ground CP2102N data sheet pin definitions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 23
5.2 CP2102N qfn24 pin definitions 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 18 17 16 15 14 13 24 pin qfn (top view) ri / clk gnd d+ d- vio vdd vregin vbus rstb nc gpio.3 / wakeup gpio.2 / rs485 cts suspend nc suspendb gpio.1 / rxt dcd dtr dsr txd rxd rts vss gpio.0 / txt figure 5.2. CP2102N qfn24 pinout table 5.2. pin definitions for CP2102N qfn24 pin number pin name description 1 ri / clk digital input. ring indicator control input (active low). digital output. clock output. 2 gnd ground 3 d+ usb data positive CP2102N data sheet pin definitions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 24
pin number pin name description 4 d- usb data negative 5 vio i/o supply power input 6 vdd supply power input / 5v regulator output 7 vregin 5v regulator input 8 vbus digital input. vbus sense input. this pin should be connected to the vbus signal of a usb network. a 5 v signal on this pin indicates a usb network connection. 9 rstb active-low reset 10 nc no connect (leave this pin floating). 11 gpio.3 / wakeup digital input/output. general purpose i/o. digital input. remote usb wakeup interrupt input. 12 gpio.2 / rs485 digital input/output. general purpose i/o. digital output. rs485 control signal. 13 gpio.1 / rxt digital input/output. general purpose i/o. digital output. receive led toggle. 14 gpio.0 / txt digital input/output. general purpose i/o. digital output. transmit led toggle. 15 suspendb digital output. this pin is driven low when the device enters the usb suspend state. 16 nc no connect (leave this pin floating). 17 suspend digital output. this pin is driven high when the device enters the usb suspend state. 18 cts digital input. clear to send control input (active low). 19 rts digital output. ready to send control output (active low). 20 rxd digital input. asynchronous data input (uart receive). 21 txd digital output. asynchronous data output (uart transmit). 22 dsr digital input. data set ready control input (active low). 23 dtr digital output. data terminal ready control output (active low). 24 dcd digital input. data carrier detect control input (active low). center gnd ground CP2102N data sheet pin definitions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 25
5.3 CP2102N qfn20 pin definitions 20 pin qfn (top view) 20 19 18 17 2 3 4 5 7 8 9 10 15 14 13 12 gpio.1 / rs485 gpio.0 / clk gnd d+ d- vdd vregin vbus rstb nc rts cts suspend wakeup gnd suspendb gpio.2 / txt gpio.3 / rxt txd rxd gnd 1 6 11 16 figure 5.3. CP2102N qfn20 pinout table 5.3. pin definitions for CP2102N qfn20 pin number pin name description 1 gpio.1 / rs485 digital input/output. general purpose i/o. digital output. rs485 control signal. 2 gpio.0 / clk digital input/output. general purpose i/o. digital output. clock output. 3 gnd ground 4 d+ usb data positive 5 d- usb data negative CP2102N data sheet pin definitions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 26
pin number pin name description 6 vdd supply power input / 5v regulator output 7 vregin 5v regulator input 8 vbus digital input. vbus sense input. this pin should be connected to the vbus signal of a usb network. a 5 v signal on this pin indicates a usb network connection. 9 rstb active-low reset 10 nc no connect (leave this pin floating). 11 suspendb digital output. this pin is driven low when the device enters the usb suspend state. 12 gnd ground 13 wakeup digital input. remote usb wakeup interrupt input. 14 suspend digital output. this pin is driven high when the device enters the usb suspend state. 15 cts digital input. clear to send control input (active low). 16 rts digital output. ready to send control output (active low). 17 rxd digital input. asynchronous data input (uart receive). 18 txd digital output. asynchronous data output (uart transmit). 19 gpio.3 / rxt digital input/output. general purpose i/o. digital output. receive led toggle. 20 gpio.2 / txt digital input/output. general purpose i/o. digital output. transmit led toggle. center gnd ground CP2102N data sheet pin definitions silabs.com | smart. connected. energy-friendly. rev. 1.0 | 27
6. qfn28 package specifications 6.1 qfn28 package dimensions figure 6.1. qfn28 package drawing table 6.1. qfn28 package dimensions dimension min typ max a 0.70 0.75 0.80 a1 0.00 0.05 a3 0.20 ref b 0.20 0.25 0.30 d 4.90 5.00 5.10 d2 3.15 3.25 3.35 e 0.50 bsc e 4.90 5.00 5.10 e2 3.15 3.25 3.35 l 0.45 0.55 0.65 aaa 0.15 bbb 0.10 ddd 0.05 CP2102N data sheet qfn28 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 28
dimension min typ max eee 0.08 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. CP2102N data sheet qfn28 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 29
6.2 qfn28 pcb land pattern x1 x2 y2 y1 c2 c1 e c0.35 figure 6.2. qfn28 pcb land pattern drawing table 6.2. qfn28 pcb land pattern dimensions dimension min max c1 4.80 c2 4.80 e 0.50 x1 0.30 x2 3.35 y1 0.95 CP2102N data sheet qfn28 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 30
dimension min max y2 3.35 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 2 x 2 array of 1.2 mm square openings on a 1.5 mm pitch should be used for the center pad. 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. 6.3 qfn28 package marking pppppppp tttttt yyww # figure 6.3. qfn28 package marking the package marking consists of: ? pppppppp C the part number designation. ? tttttt C a trace or manufacturing code. ? yy C the last two digits of the assembly year. ? ww C the two-digit workweek when the device was assembled. ? # C indicates the hardware revision. CP2102N data sheet qfn28 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 31
7. qfn24 package specifications 7.1 qfn24 package dimensions figure 7.1. qfn24 package drawing table 7.1. qfn24 package dimensions dimension min typ max a 0.70 0.75 0.80 a1 0.00 0.05 b 0.18 0.25 0.30 d 3.90 4.00 4.10 d2 2.35 2.45 2.55 e 0.50 bsc e 3.90 4.00 4.10 e2 2.35 2.45 2.55 l 0.20 0.25 0.30 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 CP2102N data sheet qfn24 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 32
dimension min typ max note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec solid state outline mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components. CP2102N data sheet qfn24 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 33
7.2 qfn24 pcb land pattern c0.25 c1 e x1 x2 y2 y1 c2 figure 7.2. qfn24 pcb land pattern drawing table 7.2. qfn24 pcb land pattern dimensions dimension min max c1 3.90 c2 3.90 e 0.50 x1 0.30 x2 2.55 y1 0.85 y2 2.55 CP2102N data sheet qfn24 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 34
dimension min max note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 4. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 7. a 2 x 2 array of 0.9 mm square openings on a 1.2 mm pitch should be used for the center pad. 8. a no-clean, type-3 solder paste is recommended. 9. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. 7.3 qfn24 package marking pppppppp tttttt yyww # figure 7.3. qfn24 package marking the package marking consists of: ? pppppppp C the part number designation. ? tttttt C a trace or manufacturing code. ? yy C the last two digits of the assembly year. ? ww C the two-digit workweek when the device was assembled. ? # C indicates the hardware revision. CP2102N data sheet qfn24 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 35
8. qfn20 package specifications 8.1 qfn20 package dimensions figure 8.1. qfn20 package drawing table 8.1. qfn20 package dimensions dimension min typ max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.18 0.25 0.30 c 0.25 0.30 0.35 d 3.00 bsc d2 1.6 1.70 1.80 e 0.50 bsc CP2102N data sheet qfn20 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 36
dimension min typ max e 3.00 bsc e2 1.60 1.70 1.80 f 2.50 bsc l 0.30 0.40 0.50 k 0.25 ref r 0.09 0.125 0.15 aaa 0.15 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 fff 0.10 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. the drawing complies with jedec mo-220. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. CP2102N data sheet qfn20 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 37
8.2 qfn20 pcb land pattern figure 8.2. qfn20 pcb land pattern drawing table 8.2. qfn20 pcb land pattern dimensions dimension min max c1 3.10 c2 3.10 c3 2.50 c4 2.50 e 0.50 x1 0.30 x2 0.25 0.35 x3 1.80 y1 0.90 y2 0.25 0.35 y3 1.80 CP2102N data sheet qfn20 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 38
dimension min max note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. 5. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thickness should be 0.125 mm (5 mils). 7. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 8. a 2 x 2 array of 0.75 mm openings on a 0.95 mm pitch should be used for the center pad to assure proper paste volume. 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. 8.3 qfn20 package marking pppp pppppp tttttt yyww # figure 8.3. qfn20 package marking the package marking consists of: ? pppppppp C the part number designation. ? tttttt C a trace or manufacturing code. ? y C the last digit of the assembly year. ? ww C the two-digit workweek when the device was assembled. ? # C indicates the hardware revision. CP2102N data sheet qfn20 package specifications silabs.com | smart. connected. energy-friendly. rev. 1.0 | 39
9. relevant application notes the following application notes are applicable to the CP2102N devices: ? an721: cp210x device customization guide this application note guides developers through the configuration process of usbxpress devices using simplicity studio [ xpress configurator ]. ? an220: usb driver customization this document and accompanying software enable the customization of the cp210x virtual com port (vcp) and usbxpress drivers. ? an197: serial communications guide for cp210x this document describes recommendations for communicating with usbx- press cp210x devices using the virtual com port (vcp) driver. ? an976: migrating from a cp2102 to a CP2102N this document guides developers on how to migrate existing systems using the cp2102 to the CP2102N. ? an169: usbxpress programmers guide this application note provides recommendations and examples for developing using the usbxpress direct-access driver. ? an807: recertifying a customized windows hck driver package this document describes the whql certification process re- quired for customized drivers. ? an223: runtime gpio control for cp210x this document describes how to toggle gpio pins from the usb host. application notes can be accessed on the silicon labs website ( www.silabs.com/interface-appnotes ) or in simplicity studio using the [ application notes ] tile. CP2102N data sheet relevant application notes silabs.com | smart. connected. energy-friendly. rev. 1.0 | 40
table of contents 1. feature list and ordering information ...................... 1 2. typical connection diagrams ......................... 2 2.1 power ................................ 2 2.2 battery charger detect ........................... 4 2.3 usb ................................. 5 3. electrical specifications ........................... 7 3.1 electrical characteristics .......................... 7 3.1.1 recommended operating conditions ..................... 7 3.1.2 power consumption ........................... 7 3.1.3 reset and supply monitor ......................... 8 3.1.4 configuration memory .......................... 8 3.1.5 internal oscillator ............................ 8 3.1.6 5 v voltage regulator .......................... 9 3.1.7 gpio ................................ 10 3.1.8 usb transceiver ............................ 11 3.2 thermal conditions ............................ 11 3.3 absolute maximum ratings ......................... 12 3.4 typical performance curves ......................... 13 4. functional description ........................... 14 4.1 usb function controller and transceiver .................... 14 4.2 universal asynchronous receiver/transmitter (uart) interface ............. 14 4.2.1 baud rate generation .......................... 15 4.3 additional features ............................ 15 4.3.1 general purpose input/outputs (gpio) ..................... 15 4.3.2 dynamic suspend ............................ 16 4.3.3 output mode ............................. 16 4.3.4 battery charging (chren, chr0, and chr1) .................. 16 4.3.5 remote wakeup (wakeup) ........................ 16 4.3.6 clock output (clk) ........................... 16 4.3.7 hardware handshaking (rts and cts) .................... 17 4.3.8 software handshaking .......................... 17 4.3.9 data throughput optimization ........................ 18 4.3.10 transmit and receive led toggles (txt and rxt) ................ 18 4.3.11 modem control (dsr, dtr, dcd, ri) .................... 19 4.3.12 rs485 (rs485) ............................ 19 4.4 drivers ................................ 19 4.4.1 virtual com port (vcp) drivers ....................... 20 4.4.2 usbxpress drivers ........................... 20 4.4.3 customization and certification ....................... 20 4.5 device customization ........................... 21 5. pin definitions .............................. 22 table of contents 41
5.1 CP2102N qfn28 pin definitions ....................... 22 5.2 CP2102N qfn24 pin definitions ....................... 24 5.3 CP2102N qfn20 pin definitions ....................... 26 6. qfn28 package specifications ........................ 28 6.1 qfn28 package dimensions ........................ 28 6.2 qfn28 pcb land pattern ......................... 30 6.3 qfn28 package marking .......................... 31 7. qfn24 package specifications ........................ 32 7.1 qfn24 package dimensions ......................... 32 7.2 qfn24 pcb land pattern .......................... 34 7.3 qfn24 package marking .......................... 35 8. qfn20 package specifications ........................ 36 8.1 qfn20 package dimensions ........................ 36 8.2 qfn20 pcb land pattern ......................... 38 8.3 qfn20 package marking .......................... 39 9. relevant application notes ......................... 40 table of contents .............................. 41 table of contents 42
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